Aldec Extends RTL Hardware Acceleration Capacity of Riviera IPT to 12 Million FPGA Gates

Henderson Nevada, May 16 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, announced today the release of Riviera IPT v12000 functional RTL hardware accelerator with a capacity of up to 12 million FPGA gates. Larger designs requiring more memory or direct support of an existing ASIC device are supported via a universal daughter board extension to accommodate system level design acceleration.

Mixed VHDL/Verilog Designs
Riviera IPT supports VHDL, Verilog and mixed-language designs and includes interfaces to C, Verisity(r) Specman Elite(tm) “e” or Synopsys(r) Vera(r) advanced testbench tools. Riviera IPT does not require custom design changes or migration to proprietary design methodologies to support RTL acceleration. Any synthesizable RTL code can be downloaded into the Riviera IPT hardware accelerator. Riviera IPT allows ASIC, SoC and FPGA design teams to reduce the system level design verification run times without changing their existing RTL design methodologies.

Performance
Riviera IPT allows design teams to decrease the functional RTL design verification time by 20 - 50x as compared to typical event-driven RTL simulators. This performance improvement virtually eliminates verification bottlenecks and speeds time-to-market from months to weeks. Riviera IPT can accommodate memories, DSPs, ASICs and other devices. It includes the ability to verify legacy designs, EDIF-based IP cores, hardware devices and HDL blocks from a single design acceleration environment.

“With 12 million gates and available expansion, we have overcome the capacity issue, additional memory requirements and support for large number of clocks that most of our customers are dealing with today,” stated Eric Seabrook, Riviera Product Marketing Manager for Aldec.

Methodology
Incremental Prototyping Technology(tm) enables the designer to verify and optimize his or her design in manageable, smaller sized blocks according to project schedules. Each block is verified in software by Riviera IPT’s built-in event-driven simulator to allow for full signal visibility and complete debugging of modules before placing them in hardware. The verified module is then placed in hardware and remains “connected” to the remainder of the design that resides in software. Using a patented closed loop technology, Riviera IPT provides event–based communication between the software and hardware components through a PCI interface. In the end, the designer has the majority of his or her design in hardware and only runs the testbench from the RTL simulator to significantly cut the verification run times.

System Configuration
Based on Aldec’s proven Riviera design environment, Riviera IPT includes an IEEE VHDL, Verilog common kernel mixed simulator, Synplify(r) Logic Synthesis, Dual Xilinx(r) Virtex II 6000 hardware accelerator board with all the drivers and a design verification manager. The system can be configured for UNIX, Linux or Windows NT/2000/XP systems.

Availability
Riviera IPT v12000 is available now and will accommodate 12 million FPGA or 3 million ASIC gates. For additional information about Riviera IPT, contact Aldec at 702-990-4400 or visit www.aldec.com.

About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.
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Active-HDL, Riviera and Riviera IPT are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners


Contact:        Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
erics@aldec.com